I was just reminiscing about the old days, remembering my childhood and how, from time immemorial until the late 1960s, electronic circuit diagrams (schematics) were hand-drawn with pencil and paper, as were circuit layouts at both the board and silicon chip level, which were also largely created by hand.
It wasn't until the early 1970s that companies like Calma, ComputerVision, and Applicon began to create special computer programs to help people in drafting departments convert hand-drawn blueprints into digital format using large digitizing tablets.
Over time, these early computer-aided drafting tools evolved into interactive programs that could be used to perform the layout of integrated circuits – that is, to describe the locations of the transistors that make up a chip and the connections between them.
Other companies, such as Racal-Redac, SCI-Cards, and Telesis, created equivalent layout programs for printed circuit boards (PCBs). Eventually, these chip and board layout programs came to be collectively known as computer-aided design (CAD) tools.
Also, in the late 1960s and early 1970s, universities and private companies began developing computer programs called simulators, first to simulate analog components and circuits, and later to simulate the digital domain. These programs allowed students and engineers to emulate the operation of electronic circuits without actually building them.
In the early 1980s, companies like Daisy, Mentor, and Valid developed computer programs that allowed engineers to capture schematics on a computer screen. These tools were used to generate textual representations of the circuit, called netlists, that described the components used and their connections. These netlists were then used to drive analog and digital simulators. Finally, the same netlists were also used to drive layout tools.
Even though they were used for design purposes, companies selling front-end tools for schematic capture and simulation classified them as Computer-Aided Engineering (CAE) tools. This was primarily because CAE companies wanted to distinguish their products from CAD tools that were originally used in drafting departments. They justified the use of the “E” in “CAE” by declaring that these tools were aimed at design engineers.
Sometime in the 1980s, all the CAE and CAD tools used to create electronic devices and systems were referred to under the “umbrella” name Electronic Design Automation (EDA), and everyone was happy (some people weren't happy, but they don't count).
One company name that “sounds familiar” to many of my colleagues is SILVACO (from SILicon VAlley COmpany). Founded in 1984, Silvaco has a long and storied history. I have always thought of Silvaco as an EDA company focused on analog custom design and analysis. More recently, I have come to know the company as an Intellectual Property (IP) provider of embedded processors, wired interfaces, bus fabrics, peripheral controllers, and cores for automotive, consumer, and IoT/sensor applications.
However, I must confess that I had completely forgotten that Silvaco was originally known for its Technology CAD (TCAD) field. “What's TCAD?” you may ask. It is a branch of EDA that models semiconductor device behavior and semiconductor manufacturing. Modeling device behavior is called device TCAD, and modeling the manufacturing process is called process TCAD. This includes modeling process steps (such as diffusion and ion implantation) and modeling electrical device behavior based on fundamental physics such as device doping profiles (yikes!).
The reason I'm rambling on about this here is because I was just talking to Dr. Babak Taheri, CEO of Silvaco. Dr. Babak surprised me right from the get-go by telling me that things have been going great since Silvaco's Initial Public Offering (IPO) in April of this year. I was surprised not because things have been going great, but because I didn't know they hadn't gone public yet. I was also happy to hear that the folks at Silvaco have been enjoying double-digit growth for the past five years, which means they must be doing something right.
Babak said that over the past 40 years, companies such as Cadence, Synopsys, Mentor (now Siemens EDA) and Silvaco have focused on helping designers develop the next generation of products more efficiently, keeping in mind that the goals are always changing: new devices, new materials, higher levels of integration, smaller process nodes.
But over the last few years, Silvaco folks have evolved their tools and technology so that it's no longer just for designers. Now, those tools are being deployed on the manufacturing floor in the form of digital twins of whole wafers and display panels. “Display panels?” you may be asking. Yes, did you know that Silvaco's EDA tools are used by 7 of the 10 largest display panel companies in the world, and our TCAD tools by 8 of those? (If you didn't already know this fun fact and gem, now you know it!)
There's hardly a story I tell these days that doesn't involve artificial intelligence (AI) and machine learning (ML), so you won't be surprised to hear that this one is no exception. The folks at Silvaco have combined their semiconductor technology expertise with AI/ML and data analytics to develop an AI-based solution for wafer-level fabrication facilities, which they call Fab Technology Co-Optimization (FTCO).
FTCO uses manufacturing data to run statistical and physics-based AI/ML software simulations to create computer models or “digital twins” of wafers that can then be used to simulate the manufacturing process.
What we're talking about here is a digital twin of all the layers that make up a wafer: transistors, metallization, etc. This digital twin is such an accurate representation that manufacturers can use it to run simulation experiments to understand and improve wafer yields without having to run physical wafers through a potentially lengthy and costly process.
“Our expertise spans from atomic-level IP to system-level IP,” Babak said (think of this as “atoms to systems”).
From atoms to systems (Source: Silvaco)
One of the amazingly intricate parts of this is that creating a wafer involves thousands of process steps and millions of parameters, many of which are tightly coupled and interrelated (i.e. adjusting one parameter “on this side” affects many parameters “on that side”, and vice versa). I naively think of this as an “nxnxn dimensional problem”, but in reality it's far from that.
To gather the data needed to create a wafer-level model with six-sigma levels of accuracy, billions of simulations would need to be run. Unfortunately, this takes so long that by the time all the data has been collected, it will no longer be useful (as human civilization as we know it will no longer exist).
To solve this conundrum, a talented team of two PhDs at Silvaco came up with a way to use AI and ML to implement something they call “intelligent sampling” – used to select the correct set of samples needed to fully represent the solution space covering wafer manufacturing. Another way to visualize this is that 25 different algorithms are used (Brownian motion, simulated annealing, genetic algorithms, etc.) all under the direction of AI/ML.
I laughed out loud when Babak concluded this part of the conversation by saying, “It's so simple,” and as I wiped the tears from my eyes, he added, “Well, the basic concept is simple, but it took us three and a half years to develop it and make it work” (which is totally believable).
Babak and I continued to discuss many related topics, but as my mind is already beginning to get confused, I will leave that discussion for another day. In the meantime, is there anything you would like to share about what you have read here?
